Headline counting and printing design device

ABSTRACT

Actuation of character keys on a typewriter produce coded pulses that are converted into binary numbers by a programmable memory, representing variations of basic linear widths in accordance with selected printing type styles. The binary number output of the memory controls a pair of counters through a gating section to display a numeric readout representing the accumulated linear width of type of selected height corresponding to the character keys actuated.

United States Patent Smith et al. 1 Jan. 16, 1973 I5 1 HEADLINE COUNTING AND PRINTING 3,248,705 4/1966 Dammann etal. ..340/172.s

DESIGN DEVICE OTHER PUBLICATIONS 75 Inventors: Leland E. Smith, Pine Bluff; Jack B. I I I 1 Johnson Lime Rock, Kenneth N IBM Tech. DIS Bulletin Vol. 5, No. 7, Dec. I962 Burks jacksonville Kenneth Automatic Editor" by Weber et al., pages 54-56 Copeland, Little Rock, all of Ark. Primary Examiner paul J. Henon [73] Assignee: Kara-Kount Incorporated, a part in- Assistant Examiner-Paul R. Woods terest Attorney-Clarence A. OBrien and Harvey B. Jacob- 22 Filed: Sept. 28, 1911 1211 Appl. No.: 184,531 ABSTRACT Actuation of character keys on a typewriter produce [52] us. (:1 ..340/172.s, l97/l8t) ended Pulses that are Converted binary numbers 51 1m.c1. G06k I5/I8 by a Programmable memmy. represemirtg variations of S h I 4 I v I Of basic linear in accordance selected I printing type styles. The binary number output of the H6) Reerences Cited memory controls a pair of counters through a gating section to display a numeric readout representing the UMTED STATES PATENTS accumulated linear width of type of selected height corresponding to the character keys actuated. 3,l65,045 l/l965 Troll 1 1 v v v ,l97/l8 X 3,244.364 4/1966 Golden .tl97/I8 X 21 Claims, 7 Drawing Figures 1 P I I 517:2 i :M candmonga7o [Alarm Section loo 22 42% H 1" I )5- I Selector l 7 208 MW mg l smmr 174 w an 1E1 m I T 1 48 E Bank [54 I /5? ll l l 145 L E B l I 6: 0U! U! I 2B 1 l 54 l go he i 56 El m w 222211" 66' /06 U8 um J -1 [02 lo Tlminp Sari/an 60 Decadlr Drive rs PATENTEDJM 16 I973 3.711.837

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Selection HEADLINE COUNTING AND PRINTING DESIGN DEVICE This invention relates to an aid for editors and caption authors in the printing industry in the form of an attachment to a conventional typewriter to assist an author in designing printing work.

Printing designers including newspaper, magazine or periodical headline writers, cutline writers and creators of all forms of advertising and printing, engage in composing literature to be used in printed form by compromising and balancing various options including the choice of words and word groups, printing type of style and size of type in order to create a desired psychological and esthetic effect. Presently, inaccurate printing design work creates manufacturing trail and error and often requires resetting and reproofing which constitutes wasted effort. It is therefore an important object of the present invention to provide an apparatus and system enabling the printing designer to obtain an exact linear measurement of printing type within a desired horizontal and vertical space utilizing a selected type style. A further object is to provide the printing designer with an attachment to an electric typewriter whereby a hard copy" may be obtained at all times for recall, classification, reset, erasure, subtraction and visualization as the designer balances and chooses between the various options of words, sizes and styles.

An author composing literature to be used in printed form dictates the styles and sizes of type to be used in given sections of a publication with each line conforming to establish limits of space, such as column width of page width. The present invention provides the author with means to compute the linear value of each line in any one of several type styles selected and in any one of various sizes that may be required. The sum of various combinations of values is computed by means of electronic memory banks and the various type styles are selected by a switch arrangement enabling the author to compute the sum of any combination of values of letters in any style or size of type programmed into the memory banks. The system of the invention utilizes multiple circuits for a practical number of memory banks plus a modular plug-in arrangement to allow a quick change of memory banks to replace obsolete type of style information or to compute various style widths, not normally used, by interchanging the memory banks. In this regard, a special programmable read-only-memory is utilized that may be erased and electronically reprogrammed in the field. Although the system may be utilized in conjunction with any measurement terms, the measurement tenns hereinafter referred to, which are utilized by the printing industry, include a PICA which is a unit of horizontal type measure equalling 0.166 inches and a POINT, which is a unit of vertical type measure equalling 0.0139 inches.

In accordance with the present invention, an author will actuate the character keys on a conventional typewriter arranged to generate coded pulses identifying the individual character key actuated. These coded input pulses are fed to a memory section within which they are converted to binary numbers representing the different basic linear widths of printing type. The binary output of the memory section controls operation of a binary counter. A decade counter is rendered simultaneously operative with the binary counter to count clock pulses. The decade counter is connected to a numeric readout display registering counts representing an accumulated linear width along a line or print. By means of a selectable divider, the clock pulses transmitted to the binary counter are divided so that the clock pulses counted by the decade counter are a predetermined multiple of the pulses counted by the binary counter. The amount by which the clock pulses are divided is selected by the operator through a point selector switch arrangement in order to introduce the type height factor aforementioned. The counting operation of both counters on the other hand is limited by the binary number output of the memory bank so as to represent the linear width of each character represented by the coded data input to the memory bank from the typewriter keyboard. Both counters are rendered simultaneously operative at the end of each programming period following sampling of the coded data from the typewriter, this being achieved through timing and gating sections. Thus, an accumulated count of the decade counter is displayed until a signal is received in response to carriage return operation of the typewriter at the end of a line of print automatically resetting the decade counter and the numeric readout display.

The type style factor is introduced by the author through a type selector switch arrangement controlling the program selection within the memory bank before receiving the coded data from the typewriter. In the event that the coded data from the typewriter is foreign to the particular type style selected, an alarm circuit is rendered operative in order to alert the author. By means of a function switch assembly, the author may change the operational mode of the decade counter and associated system components in order to make corrections. Thus, a subtract mode of operation may be obtained if an incorrect character is struck on the keyboard in order to cause the numeric display to subtract the numeric PICA value by backspacing the typewriter and striking the incorrect character again. An incorrect character may be crossed off on the typewriter copy by actuation of the slash character key after backspacing while the system is switched to a hold operational mode.

These together with other object and advantages which will become subsequently apparent reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout, and in which:

FIG. I is a perspective view showing the apparatus of the present invention as an attachment to a conventional type-writer.

FIG. 2 is a block circuit diagram corresponding to the system of the present invention.

FIG. 3 is a simplified circuit diagram illustrating with greater detail the memory section associated with the system.

FIG. 4 is a partial circuit diagram illustrating with greater detail the type style selection portion of the system.

FIG. 5 is a circuit diagram illustrating with greater detail the alarm section of the system.

FIG. 6 is a partial circuit diagram illustrating with greater detail the point selection portion of the system.

FIG. 7 is a partial circuit diagram illustrating with greater detail the mode control portion of the system.

Referring now to the drawings in detail, FIG. 1 illustrates one embodiment of the apparatus of the present invention generally denoted by reference numeral 10 positioned adjacent to a conventional electric typewriter 12 having the usual components including a keyboard 14 with character keys 16 as well as the other usual features including a spacing bar, upper case shift, carriage return key, etc. The author may accordingly produce a typewritten page in the usual fashion by inserting paper into the typewriter and actuating the character keys 16 and the other control keys. In the normal mode of operation of the apparatus 10, actuation of the character key 16 and the other control keys of the typewriter results in the registration of a PlCA number value on the numeric readout display 18 exposed through the panel of the apparatus 10. The dis play 18 is of a well known type wherein each of the four numerical digits shown is produced by illumination of seven incandescent bars. The numerical readout dis play registers the accumulated linear width value in PlCA numbers of printing type corresponding to the typewritten matter in the line being typed. At the end of the line when the carriage return control button is actuated, the numerical display 18 is automatically reset to zero so that an accumulated readout count will be available for the next line of the print.

Twelve push button switches 20 are located in horizontal alignment below the display 18 and constitute printing type style selectors. The author thus introduces the type style factor into the system operation by actuation of one of the switches 20. On the other hand, the desired height of the type is introduced as a factor in the computational operation of the system by actuation of one of the twelve POlNT size selector switches 22 horizontally arranged below the type style selector switches 20. By means of the type style selector switches 20, the system is programmed for the different base width values associated with the print characters produced on the typewritten copy by actuation of corresponding character keys 16, in the selected type style. For any selected type style, the width of the type space varies in almost the same ratio as the type varies in height or size between six points and 144 points as utilized in the printing industry in this country. In the illustrated embodiment, memory means within the system is preprograrnmed with a base value representing the six point width, in picas, of each character in all styles of type within the system. As the point value varies from one size to another, as indicated by the labeling number on the point selector switches 22, the system multiplies the programmed base accordingly. Thus, the linear width value added to the accumulated readout on the display 18 wili depend upon the character key 16 actuated, and the selector switches 20 and 22 actuated in accordance with the desired printing type style and size as will be hereafter explained in greater detail, when the system is operating in its additive mode of operation dictated by depression of the add switch 24 of the bank of function switches generally referred to by reference numeral 26.

The bank of function switches also includes a subtract switch 28 which renders the system operative to decrease the count registered by the display 18 when one of the typewriter keys is actuated. The hold switch 30 on the other hand is operative to maintain the same registered count on the display when a typewriter key is actuated. The system may be rendered inoperative so that the typewriter may be utilized in its normal fashion by actuating the off switch 32.

In the event that the data input to the system resulting from actuation of one of the character keys 16 is foreign to the particular type style selected, the author will be alerted by an alarm which may be turned off. A visual and audible alarm is provided by the alarm section. The audible alarm is turned off when the off switch 34 is actuated so that only a visual flashing alarm is produced. when the audible alarm is operative, the level of the alarm may be selected by actuation of one of the audible alarm intensity switches 36, 38 and 40. It will therefore be apparent, that the system of the present invention makes available for the printing designer, a character by character, word by word and line for line positive width count read-out in definite linear measurement standards, the readout requiring no interpolation. When combined with the electric typewriter 10, the system provides recall, classification, reset, erasure, subtraction and visualization to enable the author to balance and choose between the various word, size and style options.

As shown in PK]. 2, the system includes seven different pulse sources 42, 44, 46, 48, 50, 52 and 54. These pulses sources generate coded pulses represent ing data input from the typewriter keyboard produced by actuation of the character keys l6 and the upper case shift key. While any suitable pulse code arrangement may be utilized in association with the typewriter keys, the coded output of an IBM Selectric" Typewriter has been utilized. The spacing bar of this type of typewriter is also arranged to produce a basic pulse signal corresponding to the pulse signal output of pulse source 50. Accordingly, the spacing pulse generator component 56 is connected to the output of the pulse source 50 through diode 58 and is also connected to a timing and control section of the system generally referred to by reference numeral 60. The data input section of the system also includes a carriage return signal generator 62 connected to the timing and control section through a manual cut-out switch 64. The signal output of the carriage return signal generator 62 is operative upon return carriage operation of the typewriter to reset the display 18 as will be explained hereafter. Finally, a cycle clutch signal generator 66 feeds a signal to the timing and control section 60 whenever any of the typewriter character keys is actuated in order to initiate a sampling cycle for the memory bank generally referred to by reference numeral 68 through the timing and control section 60 as will be hereafter further explained.

The typewriter data input from the pulse sources is conditioned by a pulse conditioner component generally referred to by reference numeral 70 in FIG. 2. Each of the pulse sources includes as shown by way of example in FIG. 4, a pulse generating switch 72 connected to a source of voltage through the voltage line 74 to produce a pulse fed to one of a plurality of corresponding inverters 76 in the pulse conditioner section 70, the pulse signal being conditioned by an RC network including the grounded capacitor 78 and resistor 80 connected to the pulse signal line 80. The conditioned pulse is fed to the memory bank 68 within which it is sampled by a selected one of a plurality of memory units 82. The inverters 76 aforementioned are of a commercially available type such as manufactured by the Motorola Corporation designated as MC7404P.

With reference to FIG. 3, the memory bank 68 in the illustrated embodiment includes six of the aforemen tioned memory units 82 to which the pulse conditioner section 70 is connected in order to supply pulse input data from the typewriter to seven of the 24 terminals in each of the memory units through seven input lines 84 corresponding to the seven pulse sources aforementioned. The memory units 82 are of the electrically programmable, read-only type manufactured for example by Intel Corporation of Mountain View, California, in the form of a monolithic chip fabricated with silicon gate technology and designated as 1601/1701 MOS LS1 ROM Memory. This memory unit 82 provides a 256 word by 8 bit memory. Each memory unit is programmed ro a different particular type style enabling it to receive coded pulses from the seven different typewriter pulse sources at terminals Nos. 1, 2, 3, and 18-21. The input pulses are transported into a binary code representing a fixed basic linear value for each character width at output terminal Nos. 4 through 9 connected to a binary counter 86. Thus, following a programming period during which the input data from the typewriter is sampled by the memory bank for converting the input data into the binary number output aforementioned, the memory bank feeds a control signal in the form of a 6 bit binary number output to the binary counter 86 for controlling operation thereof by limiting the number of divided clock pulses counted by the binary counter. Each memory unit 82 is programmed to effect data conversion in accordance with different type styles. Selection is made of one of the memory units by a style type selection switch circuit 92 allowing the presence or absence of a logic one signal at an enabling circuit 88 through one of six signal lines 95. The enabling circuit is therefore programmed to supply the selected memory, by means of six signal lines 90, the data sampling signal received from timing circuit 60. Each memory unit furthermore may store two sets of information I of which is selected by the presence or absence of a logic 1 signal at terminal No. 17 which is also supplied by the type style selection switch circuit 92 through one of six signal lines 94 as shown in FIG. 3. The type selection switches 20 aforementioned are associated with the type style selection switch circuit 92 for this purpose. In the mode of operation associated with the present invention, terminal Nos. 12, 13, 15, 22 and 23 of each memory unit is connected to a positive source of voltage while terminal Nos. 16 and 24 are connected to a negative source of potential. Further, positive bias is applied to the output terminals from the positive voltage line through resistors 96. Bias voltage is also applied through resistor 98 to an output line from terminal No. in each of the memory units arranged to provide an output signal whenever the input data sampled by the selected memory unit is foreign to the type style for which the selected memory unit is programmed. This foreign character signal is applied to both the timing section 60 and an alarm section 100 with which the push button switches 34, 36, 38 and 40 are associated as aforementioned in connection with FIG. 1. The operator is thus alerted whenever the operator strikes a character key foreign to the type style selected. Finally, terminal Nos. 22 and 23 of all of the memory units are electrically interconnected for operation of the memory bank in accordance with the system of the present invention.

As hereinbefore indicated, the typewriter input data is sampled by the memory bank 68 during a programming period initiated by actuation of one of the character keys producing a signal pulse through the cycle clutch switch 66 operative to remove ground from the timing section as shown in FIG. 4 in order to initiate a timing cycle through a timing circuit 102 in the timing section as shown in FIG. 2. The timing circuit 102 delays the start of a sampling period until all pulse sources reach their proper level and then supplies a pulse signal to a NAND gate 104 which is operative to supply a signal conditioned by inverter 106 to start timing circuit 108 through which a memory enabling signal is supplied by signal line 1 10 to the memory enable gate circuit 88 from which a data sampling signal is fed to the memory bank by signal line as aforementioned. The output of timing circuit 108 through line 112 allows the binary counter 86 to accept data from the memory bank through data signal line 146. The binary data received by the binary counter is stored until the count sequence is started by a timing circuit 114. The output of the timing circuit 108 is also fed through line 112 to the timing circuit 114 from which an enable signal is fed to one terminal of NAND gate 116 by means of which a start count signal is fed by signal line 118 to a gating section 120 as shown in FIG. 2 for rendering a decade counter 122 operative simultaneously with the binary counter 86 as will be hereafter explained. However, in the event a foreign character signal is dispatched from the memory bank to the alarm section 100 through signal line 124, operation of timing circuit 126 is initiated to supply a disabling signal through line 128 to the NAND gate 116 thereby preventing establishment of any count start signal in the line 118 to the gating section 120. Thus, no readout will be registered by the display 18 in such an event. Further, the timing section 60 is operative to automatically reset the decade counter 122 as aforementioned by supply of a reset signal thereto through reset signal line 130 from NAND gate 132. An enable signal is hence applied to one terminal of the NAND gate 132 from a timing circuit 134 triggered into operation by a positive signal pulse from the carriage return switch 62. Alternatively, an electronically triggered readout clearing timing circuit 136 is operative through the NAND gate 132 to supply the reset signal in line 130 for resetting the decade counter when power is initially supplied to the system. In the event that a continuous accumulated count is desired bypassing the carriage return operation of the typewriter, the manual switch 64 may be opened in order to prevent establishment of any reset signal. The timing section 60 finally includes a timing circuit 138 through which the spacing signal from spacing control switch 56 is operative to enable the NAND gate 104 in order to initiate the programming period during which typewriter input data is sampled. The timing circuits 102, 108, 114, 126, 134, 136, and 138 may be monostable multivibrators of a type manufactured by the Motorola Corporation designated as MC74121P. The NAND gates on the other hand are of a type also manufactured by the Motorola Corporation designated as MC7400P.

Referring now to FIG. 4, the type selector circuit 92 includes the type selector switches aforementioned which are interconnected in pairs 20 and 20" consisting of two single pole, single throw switches that are ganged for respectively supplying energizing voltage to a switch illuminating lamp 140 associated with each of the switches 20 to be illuminated when the associated switch is actuated. When actuated, each switch connects a positive source of voltage to one of the input terminals of a NAND gate 142 in the memory enable gate circuit 88 so as to supply enabling signal to terminal No. 14 of a selected memory unit at the beginning of each programming period when a data sampling signal is supplied to one of the NAND gates 142 by one of the signal lines 110 from the timing section 60 as aforementioned. Sampling and conversion of data in the selected memory unit 82 may then proceed in accordance with one set of information stored therein as determined by the presence or absence of positive voltage on terminal No. 17 in the selected memory unit to which the signal line 94 is connected as shown in FIG. 4. When the type style selector switch 20' in one pair is actuated, positive voltage is blocked by diode 144 from the logic signal line 94 in order to select one set of information stored within the memory unit while actuation of the other switch 20" of a pair supplies positive voltage directly to the terminal No. 17 through signal line 94, and through the diode 144 to the NAND gate 142 thereby selecting the other set of information at the same time that the memory unit is enabled. ln the illustrated embodiment, each odd numbered selector switch 20 and following even numbered selector switch are paired as illustrated in FIG. 4 in order to select one of the six memory units 82 and the set of information stored therein to thereby sample typewriter input data during each programming period initiated by actuation of a character key 16 of the typewriter. The memory bank is hence programmed by the memory unit enabled in accordance with the desired type style.

At the end of the programming period, a binary number output is produced by the memory bank 68 as aforementioned and supplied through the 6 bit output lines 146 to the binary counter 86 for controlling operation thereof. This binary control signal limits the number of pulses counted by the binary counter 86 when triggered into operation by the start signal in line 118 from the timing section 60 through the gating section 120 as aforementioned, the pulses being supplied to the binary counter through input pulse line 148 as shown in FIG. 2. When the count of pulses to the binary counter corresponds to the binary control signal applied thereto following the programming period of the memory bank, a cycle is completed and a stop signal is produced by the binary counter 86 fed through stop signal line 150 to the gating section 120. The binary counter may be a synchronous 4 bit type manufactured by Texas Instruments designated as SN74193N.

As hereinbefore indicated with respect to FIGS. 2 and 3, the foreign character signal line 124 from the memory bank 68 is operative through the alarm section 100 to alert the operator. As shown in FIGS. 2 and 5, a

signal in line 124 is operative to trigger into operation a timing circuit 152 which in the illustrated embodiment includes a one shot multivibrator 154 of a type manufactured for example by the Motorola Corporation and designated as MC74121 by means of which the duration of an alarm signal is determined. The output of the multivibrator 154 is fed through a coupling resistor 156 to the base of transistor 158 in an alarm circuit 160 with which the selector switch circuit 162 is associated including the push button switches 34, 36, 38, and 40 aforementioned in connection with FIG. 1. Each of the switches is connected to a source of positive voltage through voltage line 164 in order to illuminate an associated switch lamp 162 when the switch is actuated. When the switch 34 is actuated, its lamp circuit is completed through the transistor 158 if switched to its conductive state in response to an output from the multivibrator 154. Thus, a foreign character signal in signal line 124 will be operative to provide a visual flashing signal through the lamp associated with the off switch 34 with actuated, actuation of this switch preventing any audible alarm signal from being established. When the lamp circuit associated with the off switch 34 is opened, the collector output of transistor 158 is completed through an audible alarm device 168 in series with one of three parallel connected resistors 170 respectively connected to the positive voltage line 164 through an associated one of the switches 36, 38, and 40. Thus, the value of the resistors 170 will determine the output level of the audible alarm device 168 causing operation thereof together with flashing operation of an associated switch lamp whenever the transistor 158 is switched to a conductive state by the output from the multivibrator 154. The operator may thereby select a visible or audible alarm or both as well as the output level of the audible alarm when utilized.

The divider 210 is a pulse rate control through which pulses are fed to the binary counter 86 through a gating section 172 and pulse line 148 at a selectively varied rate as compared to the pulses directly applied from a clock 174 to the readout section 176 by the mode control portion 178 of the gating section. The gating section 172 also includes a dual flip flop component 180 of a type manufactured by the Motorola Corporation designated as MC7476P. A start count signal pulse from the timing section 60 is supplied by signal line 118 to one preset terminal 182 of section 180A of the flip flop which raises terminal 184 to logic one. This in turn enables NAND gate 186 to preset flip flop section 180B upon receipt of the next divided clock pulse, allowing terminal 196 to enable NAND gate 190 to pass divided clock pulse to the binary counter through line 148. Also, the divided clock pulse is passed simultaneously by NAND gate 198 through section 178 to the decade counter 122. The pulse conducted by signal line 148 to the binary counter is also received at terminal 194 of the dual flip flop section 180A to clear through terminal 184, disabling the NAND gate 186. As a result of the foregoing arrangement, both counters 86 and 122 are activated simultaneously to start counting pulses received while both counters stop counting when the stop signal is supplied to terminal 202 from the binary counter 86 through stop signal line 150. The gate 200 inverts the clock signal and holds the circuit at the proper logic level for transmission of the clock signal to NAND gates 204 and 206 respectively connected to the additive and subtractive terminals of the decade counter 122. One or the other of the gates 204 and 206 is rendered operative to pass the clock signal by the function switch assembly 26 in order to control the operational mode of the readout section 176.

While the clock signal is directly transmitted through the gating section to the readout section at a predetermined rate, it is divided by a selected amount under control of the operator through the point selector switches 22 aforementioned by means of a matrix assembly 208 and the aforementioned selectible divider arrangement 210 as diagrammatically shown in H6. 2. Thus, the number of pulses counted by the readout section will be some selected multiple of the pulses counted by the binary counter 86 during the same time interval. Since the number of pulses counted by the binary counter 86 following each data input cycle from the typewriter, represents a linear width value for a selected type style, this value is modified in accordance with the type size selection by dividing the block pulses accordingly. In the illustrated embodiment, the clock pulses counted by the readout section will be the product of the number of pulses counted by the binary counter and the selected point value divided by sixtenths. As shown in FIG. 6, each point selector switch 22 includes a pair of ganged switch elements connected to a positive voltage line 212, one of the switch elements thereby completing an energizing circuit through the lamp 214 in order to illuminate the actuated switch while the other switch element connects the positive voltage line to one of six terminals associated with each of two diode matrix components 216 interconnected in series. These matrix components are of type manufactured by the Harris Semiconductor Division of Harrislntertype Corporation designated as HM 1-0186. Thus, by means of the 12 point selector switches 22, the operator is able to load 12, 8 bit binary numbers into the divider arrangement 210 by accordingly loading the matrix components. The output of the matrix component is connected in parallel to a pair of circuit sections 218 and 220 in the divider arrangement 210. These circuit sections are synchronous, 4 bit counters of a type manufactured by Texas Instrument Company designated as SN74l93. The circuit sections are capable of dividing any number between one and 256 depending on the binary number loaded into them. Thus, the clock pulses fed to the divider section are divided by a preset amount to modify the clock pulse rate fed through the binary counter. When the binary counter receives a specific number of pulses from the selectible divider through the gating section as aforementioned, in accordance with the program dictated thereto from the memory bank, a stop pulse is dispatched through line 150 to the flip flop of the gating section in order to terminate operation of the readout section until another data input cycle is initiated by actuation of the next character key of the typewriter.

In the normal operation of the system, the additive function switch 24 is actuated as aforementioned thereby connecting the voltage supply line 222 from the power supply component 224 of the system to the switch lamp 226 associated with the add switch 24 as shown in FIG. 7. The lamp circuit is thereby completed in order to illuminate the actuated add switch. At the Ill same time, the add switch connects the voltage supply line through the gating section in the add terminal 242 of the first decade counter 240. The decade counter component 122 consists of five series connected synchronous 4 bit counters 240 which provide an accumulated count output from the last four counters through decoder drivers 228 to activate the proper segments of a seven bar readout display It] as aforementioned. The decoder drivers are of a type manufactured by the Radio Corporation of America designated RCA 2502B. The decade counter also has subtract terminal 230 to which the clock pulses are alternatively fed upon actuation of the subtract switch 28 connecting the voltage supply line 222 to the subtract terminal 230 through the gating section 120 and at the same time completing an energizing circuit through the lamp 232 associated with the subtract switch. When the hold switch 30 is actuated, its associated lamp 234 is illuminated and no voltage is supplied to the gating section for passage of clock pulses to the decade counter. The add switch 24, the subtract switch 28, and the hold switch 30 are thereby operative to select the operational mode of the system. When the off switch 32 is actuated, it disconnects the power supply component 224 from the power supply lines 236 and 238 thereby shutting down the system without-however affecting operation of the typewriter.

It will be apparent from the foregoing description, that the system of the present invention allows selection of type style and size by simple actuation of selector switches 20 and 22 as shown in FlG. 1. It incorporates an audible and/or visual alarm to indicate when a character has been used which is foreign to the style of type selected. It also allows correction of the readout resulting from typing errors by the simple actuation of switch 28 to subtract the value of the erroneous character by restriking of the incorrect character key. Also, the operator may switch the system to a hold mode through switch 30 while typing in a character, such as a slash character over an erroneously struck character, before the system is reset. By replacement or exchange of modular memory units, the system may be reprogrammed in order to introduce for example a new kind of type style.

The foregoing is considered as illustrative only of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the invention.

What is claimed as new is as follows:

1. In combination with a typewriter having a keyboard and means for generating a plurality of coded input pulses representing corresponding characters on the keys of the keyboard in response to actuation of said keys, a computing device comprising a pair of counters, memory means connected to the input pulse generating means for converting said input pulses into corresponding control signals programming one of the counters during a sampling period, a source of clock pulses, readout display means connected to the other of the counters for registering an accumulated count of said clock pulses, gating means connected to the counters for simultaneously transmitting the clock pulses thereto at different pulse rates, selection means connected to the gating means for varying the pulse rate of the clock pulses transmitted to said one of the counters, timing means interconnected between the input pulse generating means and the gating means for rendering the counters operative simultaneously following said programming of said one of the counters by the memory means, and count limit means responsive to completion of said programming for limiting supply of clock pulses to said one of the counters.

27 The combination of claim 1 wherein the memory means comprises a plurality of interconnected memory units each having input terminals connected to the input pulse generating means and binary output terminals connected to said one of the counters, and type style selecting means connected to the memory means for selecting one of the memory units to which the input pulses are applied, each memory unit storing at least one program representing the basic linear widths of characters for a given style of type.

3. The combination of claim 2 including foreign character alarm means connected to the memory means for producing an alert in response to input pulses for which the selected one of the memory units is programmed, whereby actuation of a key corresponding to a non-existent character in the selected type style, is registered by the alarm means.

47 The combination of claim 3 including reset means connecting the timing means to said other of the counters for resetting the count to zero in response to carriage return operation of the typewriter.

5. The combination of claim 4 wherein said selection means includes divider means for dividing the clock pulses transmitted to said one of the counters by a selected amount representing different type heights.

6. The combination of claim 5 wherein the count of divided clock pulses is limited by the control signals to a number presenting the linear widths in a selected type style corresponding to the characters on the keys of the keyboard.

7. The combination of claim 1 wherein said selection means includes divider means for dividing the clock pulses transmitted to said one of the counters by a selected amount representing different type heights.

8. The combination of claim 7 wherein the count of divided clock pulses is limited by the control signals to a number representing the linear widths in a selected type style corresponding to the characters on the keys of the keyboard.

9. The combination of claim 8 wherein the memory means comprises a plurality of interconnected memory units each having input terminals connected to the input pulse generating means and binary output terminals connected to said one of the counters, and type style selecting means connected to the memory means for selecting one of the memory units to which the input pulses are applied, each memory unit storing at least one program representing the basic linear widths of characters for a given style of type.

10. In combination with a typewriter having a keyboard and means for generating a plurality of coded input pulses representing the characters on the keys of the keyboard, a computing device comprising a pair of counters, memory means connected to the pulse generating means for converting said input pulses into corresponding control signals programming one of the counters, a source of clock pulses, readout display means connected to one of the counters for registering an accumulated count of said clock pulses, gating means connected to the counters for simultaneously transmitting the clock pulses to the other of the counters at a preselected rate representing type height, tim' ing means for rendering the counters operative simultaneously following said programming of said one of the counters by the memory means, and count limiting means responsive to completion of said programming for transmitting said control signals from the memory means to said one of the counters to limit counting of the clock pulses by an amount representing variations of the basic linear widths corresponding to a selected type style.

I]. In combination with a plurality of input sources from which predetermined pulse train signals are derived representing different input values, means for controlling operation of a binary counter comprising a plurality of interconnected memory units each having input terminals respectively connected to said input sources and output terminals connected to the binary counter for programming operation thereof, timing means connected to the memory units for sampling the pulse train signals during a predetermined programming cycle, means responsive to said programming cycle for rendering one of the memory units operative to convert the sampled pulse train signals into binary bit signals at said output terminals, a clock source of reference signals, gate means connected to the timing means for transmitting said reference signals to the binary counter in response to termination of the programming cycle, and means connecting the output terminals of the memory units to the binary counter for producing an output signal therefrom in response to reception of a number of the reference signals dictated by the binary bit signals representing a selected function of the input values.

12. The combination of claim 11 including second counter means connected to the gate means for counting the reference signals simultaneously with the binary counter at a more rapid pulse rate.

13. The combination of claim 12 including pulse rate control means connected to the gate means and the clock source for selecting the relative pulse rates of the reference signals received by the binary counter and the second counter means.

14. The combination of claim 13 including selector means connected to the means rendering one of the memory units operative for selecting said one of the memory units and the information stored therein.

15. The combination of claim 14 wherein each of said memory units is of the electrically programmable read only type.

16. The combination of claim 15 wherein each of the memory units includes another terminal from which an alarm signal is obtained in response to one of the pulse train signals for which the selected one of the memory units is programmed to indicate an input value non-existent with respect to the selected one of the memory units.

17. The combination of claim 11 including selector means connected to the means rendering one of the 20. The combination of claim I] wherein each of said memory units is of the electrically reprogrammable read only type.

21. The combination of claim 20 wherein each of the memory units includes another terminal from which an alarm signal is obtained in response to one of the pulse train signals for which the selected one of the memory units is programmed to indicate an input value non-existent with respect to the selected one of the memory units. 

1. In combination with a typewriter having a keyboard and means for generating a plurality of coded input pulses representing corresponding characters on the keys of the keyboard in response to actuation of said keys, a computing device comprising a pair of counters, memory means connected to the input pulse generating means for converting said input pulses into corresponding control signals programming one of the counters during a sampling period, a source of clock pulses, readout display means connected to the other of the counters for registering an accumulated count of said clock pulses, gating means connected to the counters for simultaneously transmitting the clock pulses thereto at different pulse rates, selection means connected to the gating means for varying the pulse rate of the clock pulses transmItted to said one of the counters, timing means interconnected between the input pulse generating means and the gating means for rendering the counters operative simultaneously following said programming of said one of the counters by the memory means, and count limit means responsive to completion of said programming for limiting supply of clock pulses to said one of the counters.
 2. The combination of claim 1 wherein the memory means comprises a plurality of interconnected memory units each having input terminals connected to the input pulse generating means and binary output terminals connected to said one of the counters, and type style selecting means connected to the memory means for selecting one of the memory units to which the input pulses are applied, each memory unit storing at least one program representing the basic linear widths of characters for a given style of type.
 3. The combination of claim 2 including foreign character alarm means connected to the memory means for producing an alert in response to input pulses for which the selected one of the memory units is programmed, whereby actuation of a key corresponding to a non-existent character in the selected type style, is registered by the alarm means.
 4. The combination of claim 3 including reset means connecting the timing means to said other of the counters for resetting the count to zero in response to carriage return operation of the typewriter.
 5. The combination of claim 4 wherein said selection means includes divider means for dividing the clock pulses transmitted to said one of the counters by a selected amount representing different type heights.
 6. The combination of claim 5 wherein the count of divided clock pulses is limited by the control signals to a number presenting the linear widths in a selected type style corresponding to the characters on the keys of the keyboard.
 7. The combination of claim 1 wherein said selection means includes divider means for dividing the clock pulses transmitted to said one of the counters by a selected amount representing different type heights.
 8. The combination of claim 7 wherein the count of divided clock pulses is limited by the control signals to a number representing the linear widths in a selected type style corresponding to the characters on the keys of the keyboard.
 9. The combination of claim 8 wherein the memory means comprises a plurality of interconnected memory units each having input terminals connected to the input pulse generating means and binary output terminals connected to said one of the counters, and type style selecting means connected to the memory means for selecting one of the memory units to which the input pulses are applied, each memory unit storing at least one program representing the basic linear widths of characters for a given style of type.
 10. In combination with a typewriter having a keyboard and means for generating a plurality of coded input pulses representing the characters on the keys of the keyboard, a computing device comprising a pair of counters, memory means connected to the pulse generating means for converting said input pulses into corresponding control signals programming one of the counters, a source of clock pulses, readout display means connected to one of the counters for registering an accumulated count of said clock pulses, gating means connected to the counters for simultaneously transmitting the clock pulses to the other of the counters at a preselected rate representing type height, timing means for rendering the counters operative simultaneously following said programming of said one of the counters by the memory means, and count limiting means responsive to completion of said programming for transmitting said control signals from the memory means to said one of the counters to limit counting of the clock pulses by an amount representing variations of the basic linear widths corresponding to a selected type style.
 11. In combination with a plurality of input sources from which predetermined pulse train signals are derived representing different input values, means for controlling operation of a binary counter comprising a plurality of interconnected memory units each having input terminals respectively connected to said input sources and output terminals connected to the binary counter for programming operation thereof, timing means connected to the memory units for sampling the pulse train signals during a predetermined programming cycle, means responsive to said programming cycle for rendering one of the memory units operative to convert the sampled pulse train signals into binary bit signals at said output terminals, a clock source of reference signals, gate means connected to the timing means for transmitting said reference signals to the binary counter in response to termination of the programming cycle, and means connecting the output terminals of the memory units to the binary counter for producing an output signal therefrom in response to reception of a number of the reference signals dictated by the binary bit signals representing a selected function of the input values.
 12. The combination of claim 11 including second counter means connected to the gate means for counting the reference signals simultaneously with the binary counter at a more rapid pulse rate.
 13. The combination of claim 12 including pulse rate control means connected to the gate means and the clock source for selecting the relative pulse rates of the reference signals received by the binary counter and the second counter means.
 14. The combination of claim 13 including selector means connected to the means rendering one of the memory units operative for selecting said one of the memory units and the information stored therein.
 15. The combination of claim 14 wherein each of said memory units is of the electrically programmable read only type.
 16. The combination of claim 15 wherein each of the memory units includes another terminal from which an alarm signal is obtained in response to one of the pulse train signals for which the selected one of the memory units is programmed to indicate an input value non-existent with respect to the selected one of the memory units.
 17. The combination of claim 11 including selector means connected to the means rendering one of the memory units operative for selecting said one of the memory units and the information stored therein.
 18. The combination of claim 17 wherein each of said memory units is of the electrically reprogrammable read only type.
 19. The combination of claim 18 wherein each of the memory units includes another terminal from which an alarm signal is obtained in response to one of the pulse train signals for which the selected one of the memory units is programmed to indicate an input value non-existent with respect to the selected one of the memory units.
 20. The combination of claim 11 wherein each of said memory units is of the electrically reprogrammable read only type.
 21. The combination of claim 20 wherein each of the memory units includes another terminal from which an alarm signal is obtained in response to one of the pulse train signals for which the selected one of the memory units is programmed to indicate an input value non-existent with respect to the selected one of the memory units. 